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cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 1/12 em5303qp c y s t ek product s pecification 5v/12v synchronous buck pwm controller em5303/a general description em5303/a is a synchronous rectified pwm controller operating with 5v or 12v supply voltage. this device operates at 200/300 khz and provi des an optimal level of integratio n to reduce size and cost of the power supply. this part includes internal soft start, internal compensation netw orks, over current protection, under voltage protection, and shutdown function. this part is available in psop-8 package. features z operate from 5v to 12v voltage supply z 0.6v v ref with 1.5% accuracy z voltage mode pwm control z 200khz or 300khz fixed frequency oscillator z 0% to 80% duty cycle z internal soft start z over current protection z integrated bootstrap diode z adaptive non-overlapping gate driver z under voltage protection z over voltage protection applications z notebook & netbook z graphic cards & mb z low voltage logic supplies ordering information part number package frequency em5303qp psop-8 200khz EM5303Aqp psop-8 300khz http://
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 2/12 em5303qp c y s t ek product s pecification pin configuration typical application circuit pin assignment pin name pin no. pin function boot 1 bootstrap supply for the floating upper gate driv er. connect the bootstrap capacitor c boot between boot pin and the phase pin to form a bootstrap circuit. the bootstrap capacitor provides the charge to turn on the upper mosfet. typical values for c boot range from 0.1uf to 0.47uf. ensure that c boot is placed near the ic. ugate 2 upper gate driver output. connect this pin to the gate of upper mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper mosfet has turned off. gnd 3 signal and power ground for the ic. all voltages levels are measured with respect to this pin. tie this pin to the ground island/plane through the lowest impedance connection available.
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 3/12 em5303qp c y s t ek product s pecification lgate 4 lower gate driver output. connect this pin to the gate of lower mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turn off. vcc 5 supply voltage. this pin provides the bias supply for the em5303/a and the lower gate driver. the supply voltage is interna lly regulated to 4vdd for internal control circuit. connect a well-decoupled 4.5v to 13.2v supply voltage to this pin. ensure that a decoupling capacitor is placed near the ic. fb 6 feedback voltage. this pin is th e in verting inpu t to the erro r am plif ier. a resisto r divider from the output to gnd is us ed to set the regulation voltage. en 7 enable pin. pulling this pin lower than 0.3v disa bles the controller and causes the oscillator to stop, the ugate and l gate outputs to be held low. phase 8 phase switch node. connect this pin to the s ource of the upper mosfet and the drain of the lower mosfet. this pin is used as the sink for the ugate driver, and to monitor the voltage drop across the lowe r mosfet for over current protection. this pin is also monitored by the adaptive shoot -through protection circ uitry to determine when the upper mosfet has turned off. a schottky diode betw een this pin and ground is recommended to reduce negative tr ansient voltage which is common in a power supply system. function block diagram 5 ugate 0.3v en boo t vcc soft start + - - fb ea reference enable ramp gate control logic pwm phase lgate gnd vcc por internal regulator v ocp oscillator 1 2 8 4 3 6 7 vcc 17v fb 75% vref otp fb 130% vref
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 4/12 em5303qp cystek product specification absolute maximum ratings (note 1) z supply voltage, vcc--------------------------------------------------------- -0.3v to 16v z phase to gnd dc------------------------------------------------------------------------------- -5v to 16v <200ns------------------------------------------------------------------------- -10v to 32v z boot to phase------------------------------------------------------------------------ 16v z boot to gnd dc--------------------------------------------------------------------- -0.3v to phase+16v <200ns------------------------------------------------------------------------- -0.3v to 42v z ugate------------------------------------------------------- phase ? 0.3v to boot + 0.3v z lgate----------------------------------------------------------------- -0.3v to vcc + 0.3v z en & fb-------------------------------------------------------------------------- -0.3v to 6v z power dissipation, pd @ ta = 25 c, psop-8 -------------------------------------- 0.625w z package thermal resistance, ja, psop-8 (note 2)-------------------------- 160 c/w z junction temperature--------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.)-------------------------------------------- 260 c z storage temperature range----------------------------------------------- 65 c to 150 c z esd susceptibility (note3) hbm (human body mode)------------------------------------------------------------ 2kv mm (machine mode)----------------------------------------------------------------- 200v recommended operating conditions (note5) z supply voltage, v cc ------------------------------------------------------- 4.5v to 13.2v z junction temperature --------------------------------------------------- -40 c to 125 c z ambient temperature ---------------------------------------------------- -40 c to 85 c electrical characteristics v cc =12v, t a =25 , unless otherwise specified parameter symbol test conditions pin min typ max units supply input section supply voltage v cc 5 4.5 13.2 v supply current i cc lgate, ugate open, switching. 5 3 ma quiescent supply current i ccq no switching. 5 2 ma power on reset threshold v ccrth 5 4 4.2 4.4 v power on reset hysteresis v cchys 5 0.2 v internal oscillator em5303 170 200 230 khz free running frequency f sw EM5303A 255 300 345 khz ramp amplitude v osc 1 v p-p error amplifier open loop dc gain a o guaranteed by design 55 70 db gain-bandwidth product gbw guaranteed by design 10 mhz slew rate sr guaranteed by design 3 6 v/us trans-conductance g m guaranteed by design 0.2 0.7 ms
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 5/12 em5303qp c y s t ek product s pecification pwm controller gate drivers upper gate sourcing current i ug_src v boot - v phase = 12v, v boot - v ugate = 6v 2 -1 a upper gate sinking current i ug_snk v boot - v phase = 12v, v ugate ? v phase = 6v 2 1.5 a upper gate r ds(on) sinking r ug_snk v boot - v phase = 12v, v ugate ? v phase = 0.1v 2 2 4 ? lower gate sourcing current i lg_src v cc ? v lgate = 6v 4 -1 a lower gate sinking current i lg_snk v lgate = 6v 4 1.5 a lower gate r ds(on) sinking r lg_snk v lgate = 0.1v 4 2 4 ? phase falling to lgate rising delay v cc = 12v; v phase < 1.2v to v lgate > 1.2v 30 90 ns lgate falling to ugate rising delay v cc = 12v; v lgate < 1.2v to (v ugate - v phase ) > 1.2v 30 90 ns reference voltage nominal feedback voltage v fb 6 0.591 0.6 0.609 v enable voltage en enable threshold v en 7 0.3 0.35 v protection section fb under voltage protection v fb_uvp fb falling 6 55 65 75 % fb over voltage protection v fb_ovp fb rising 6 115 130 145 % vcc over voltage protection v cc_ovp 5 16 17 18 v over current threshold v ocp -425 -375 -325 mv soft-start interval t ss 2.4 3.6 5.4 ms temperature shutdown t sd guaranteed by design 150 165 note 1. stresses listed as the above ?absolute maximum ratings? ma y cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. no te 2 . ja is measured in the natural convection at t a =25 o c on a 4-layers high effective thermal conductivity test board with minimum copper area of jede c 51-7 thermal measurement standard. the case point of jc is on the expose pad for psop-8 package. note 3. ja psop-8 packages is 52 c /w on jedec 51-7 (4 layers,2s2p) thermal test board with 50mm 2 copper area. note 4. devices are esd sensitive. handlin g precaution is recommended. note 5. the device is not guaranteed to function outside its operating conditions.
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 6/12 em5303qp c y s t ek product s pecification typical operating characteristics power on waveform turn on from en v in =12v v out =1.2v c out =1000uf no load. v in =12v v out =1.2v c out =1000uf no load. turn off from en switching waveforms: ugate turn on v in =12v v out =1.2v c out =1000uf i out =6a. v in =12v i out =10a switching waveforms: ugate turn off power sequencing operation v in =12v i out =10a v cc =12v ready v out = 1.2v, c out = 1000uf, no load . v en v out phase i lx v in v out phase i lx v out v en phase i lx ug a t e phase uga t e - phase lg a t e ug a t e phase phase lg a t e v in v out phase
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 7/12 em5303qp c y s t ek product s pecification load transient response over current protection v in =12v v out =1.2v c out =1000uf. v in =12v, v out =1.2v, c out =1000uf. output short ground over current protection load regulation output volta g e deviation ( % ) v in =12v, v out =1.2v, c out =1000uf. turn on to short circuit output current (a) line regulation sw itching frequency vs. input voltage phase v out i out phase v out i out i out v out phase switchin g fr equen c y de viation ( % ) outpu t v o lt a g e de viation (%) input voltage (v) input voltage (v)
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 8/12 em5303qp c y s t ek product s pecification s w itching frequency vs. junction temperature output voltage vs. junction temperature switching frequency deviation (%) output voltage deviation (%) junction temperature ( ) junction temperature ( )
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 9/12 em5303qp c y s t ek product s pecification functional description em5303/a is a voltage mode synchronous buck pwm cont roller. the compensation circuit is implemented internally to minimize th e external component count. this devi ce provides complete protection function such as over current protection, under voltage protection and over voltage protection. supply voltage the v cc pin provides the bias supply of em5303/a contro l circuit, as well as lower mosfet?s gate and the boot voltage for the upper mosfet?s gate. a mi nimum 0.1uf ceramic capacitor is recommended to bypass the supply voltage. power on reset to let em5303/a start to operation, v cc voltage must be higher than its por voltage even when en voltage is pulled higher than enable high voltage. typical por voltage is 4.2v. enable to let em5303/a start to operation, en voltage must be higher than it s enable voltage. typical enable voltage is 0.3v. soft start em5303/a provides soft start function internally. the fb voltage will track the internal soft start signal, which ramps up from zero during soft start period. ocp, over current protection the over current function protects the converter from a shorted output by using lower mosfet?s on-resistance to monitor the current. the ocp leve l can be calculated as the following equation: ds(on) ocp ocp r v i ? = when ocp is triggered, em5303/a will shut down the converter and cycles the soft start function in a hiccup mode. if over current condition still exist af ter 3 times of hiccup, em5303/a will shut down the controller and latch. uvp, under voltage protection the fb voltage is monitored for under voltage protection. the uvp threshold is typical 0.4v. when uvp is triggered, em5303/a will shut down the converter and cycles the soft start function in a hiccup mode. ovp, over voltage protection the fb voltage is monitored for over voltage protect ion. the ovp threshold is typical 0.8v. when ovp is triggered, em5303/a will turn off upper mosfet and turn on lower mosfet. output inductor selection the output inductor is select ed to meet the ou tput voltage ripple requirement s and minimize the response time to the load transient. the inductor value determ ines the current ripple and voltage ripple. the ripple current is approximately the following equation: sw in out out in l f * v v l v v i ? ? =
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 10/1 2 em5303qp c y s t ek product s pecification output capacitor selection an output capacitor is requi red to filter the output and supply the lo ad transient. the selection of output capacitor depends on the output ripple voltage. the output ripple voltage is approximately bounded by the following equation: input capacitor selection use a mix of input bypass capacitor s to control the voltage overshoo t across the mosfet. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper mosfet turn on. place the small ceramic capacitors physically close to the mosfets and between the drain of the upper mosf et and the source of the lower mo sfet. the important parameters of the input capacitor are the voltage rating and the rms current ra ting. the capacitor vo ltage rating should be at least 1.25 times greater than the maximum i nput voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating require ment can be expressed as the following equation: d) - d(1 i i out rms = for a through hole design, several electrolytic capacito rs may be needed. for su rface mount designs, solid tantalum capacitors can also be used but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of ha ndling the surge current at power-up. some capacitor series available from reputable ma nufacturers are surge current tested. power mosfet selection the em5303/a requires two n-channel power mo sfets. these should be selected based upon on-resistance, breakdown voltage, gate supply requi rement, and thermal management requirements. in high current applications, the mosfet power dissi pation, package selection and heat sink are the dominate design factor. the power dissipation includes two loss components: conduction loss and switching loss. the conduc tion losses are the largest component of power dissipation for both the upper and lower mosfets. these losses are distributed betw een the two mosfets according to duty factor. the power dissipations in the two mosfets are approximately the following equation: sw sw in out ds(on) out 2 upper t f v i d * r * i pd * * * * 5 . 0 + = d ) - (1 * r * i pd ds(on) out 2 lower = where d is the duty cycle, t sw is the combined switch on and off time.
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 1 1/ 12 em5303qp c y s t ek product s pecification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. 6 minutes max. 8 minutes max. time 25 c to peak temperature note : all temperatures refer to topside of t he package, measured on the package body surface.
cys tech electronics corp. s pec. no. : c551 qp issued date : 20 10.10.25 revised date : page no. : 12/1 2 em5303qp c y s t ek product s pecification psop-8 dimension *:typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1850 0.2008 4.70 5.10 h 0.0157 0.0327 0.40 0.83 b 0.1457 0.1614 3.70 4.10 i 0.0075 0.0102 0.19 0.26 c 0.2283 0.2441 5.80 6.20 j 0.0098 0.0197 0.25 0.50 d 0.0130 0.0200 0.33 0.51 k 0 8 0 8 e 0.05* 1.27 * m 0.0764 0.0980 1.94 2.49 f 0.0472 0.0638 1.20 1.62 n 0.0764 0.0980 1.94 2.49 g 0.0032 0.0110 0.08 0.28 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . marking: device name date code 8-l ead pso p-8 plasti c surface mou n ted packa g e cys t ek pa ckage code: q p date code device name

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